Cdv/dt Induced Turn-on in Synchronous Buck Regulators

Cdv/dt induced turn-on of the synchronous MOSFET deteriorates performance in synchronous buck regulators. We will discuss this problem and provide several solutions that can reduce the effects. SYNCHRONOUS BUCK REGULATOR Synchronous buck topology is becoming popular in powering ultra-fast CPU cores. A standard buck circuit is shown in Figure 1(a) and a synchronous buck is shown in Figure 1(b). As shown in Figure 1(b), by replacing the freewheeling diode with a MOSFET, the standard buck regulator is converted into a synchronous buck topology. This topology will provide higher efficiency than the standard buck circuit. Typically a Schottky diode is paralleled with MOSFET Q2 but is omitted from this paper because it is not required to understand and solve the Cdv/dt induced turn-on problem. Ideal synchronous buck regulator waveforms are illustrated in Figure 2(a). The control MOSFET Q1 is used to regulate the output voltage by adjusting its duty factor. When Q1 is turned off, the inductor current of Lout continues to flow through either the synchronous MOSFET Q2 or its body diode. Figure 1. (a) Standard buck topology. (b) Synchronous buck topology. Figure 2. (a) Ideal waveforms in a synchronous buck voltage regulator; (b) waveforms due to Cdv/dt induced turn-on at Q2. Dead-times, td12 and td21 as shown in Figure 2(a) are introduced to prevent the cross conduction that would occur if Q1 and Q2 gate drive signals were overlapped. During the dead time, only the body diode of Q2 conducts and the drain voltage of Q2 is clamped to minus one diode